The present invention relates to a linked component extraction circuit for checking a linking state of pixels of logic "1" in a binary figure having logic values of "1" and "0" stored in a two-dimensional image memory in an image processor and for sequentially assigning numbers (labels) to the pixels of logic "1" to generate an output image.
Demand often arises in graphic processing to check the characteristics of a specific portion of a figure. For example, in an image including cells in a medical image, there is a demand for checking characteristics of a specific cell image. In this case, when numbers (labels) are assigned to areas corresponding to the cells in the image, as shown in FIG. 1, a desired cell area can be extracted by designating only the corresponding number (label).
A conventional circuit suitable for such processing is described in Japanese Patent Publication No. 57-6620 and is known as a "linked component extraction circuit comprising: a two-dimensional image memory for storing a binary image; a linked component detector for sequentially reading out pixel data from the image memory to extract a linked component of the binary image and for assigning numbers to the extracted linked components in accordance with a predetermined order; a two-dimensional multi-value memory having the same capacity as that of the binary image; means for storing the numbers at addresses of the multi-value memory which correspond to pixel positions, the numbers being assigned by the linked component detector in units of pixel data; and table memory for designating that linked components represented by two different numbers are identical when the two different numbers assigned by the linked component detector represent identical linked components". In such a linked component extraction circuit, different numbers are often assigned to pixels of identical linked components for a complicated figure. In this case, data conversion is required to assign an identical number to pixels of identical linked components. In other words, the table memory must be updated. The more the figure is complicated, the more the data updating is complicated. During data updating, the next pixel processing cannot be performed, and the processing rate is lowered, resulting in inconvenience. In addition, linked components cannot be detected at a predetermined detection rate, so "handshaking" or the like for data transfer is required. As a result, the processing rate is further lowered.